The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, stricter demands have been placed on multiple-patterning processes. For example, smaller devices which use multiple-patterning on multiple layers require that the alignment between various layers in the semiconductor device (also referred to as overlay) be precise and accurate. In other words, it is desirable to reduce the overlay error. Although existing multiple-patterning methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.